A varactor is a voltage-controlled capacitor, wherein the capacitance of the capacitor is directly related to the voltage applied to its terminals. MOS varactors, that is, a varactor implemented on a metal oxide semiconductor device, have particular application in radio frequency (RF) and millimeter wave (mmW) local oscillators, which in turn find application in radar and telecommunications technologies, among others. For example, the past several years have witnessed the rapidly expanding commercial application of the mmW band in 60 GHz wireless personal area networking (WPAN) systems and in 77 GHz automotive radar systems.
The phase noise of local oscillators, which influences the overall performance of the system in which they are implemented, is strongly dependent, especially in the 60 GHz and above frequency ranges, on the quality factor (Q-factor) of the MOS varactor in the local oscillator. The Q-factor of a MOS varactor can be expressed as:
  Q  =      1          ω      ⁢                          ⁢              CR        s            where ω is the frequency, C is the capacitance, and Rs is the series resistance (which itself has two components: gate resistance and channel resistance of the MOS varactor). As is apparent, as frequency increases, the Q-factor decreases. Thus, for applications such as those noted above where a higher frequency is required, it becomes necessary to reduce the series resistance in order to maintain a suitable Q-factor on par with MOS varactors that operate at lower frequencies.
The series resistance of a MOS varactor is highly dependent on the layout of the MOS varactor, that is, the dimensions of its gate and channel structures, as well as the positioning of its gate and channel structures with respect to one another. Thus, considerable effort has been expended in the past few years in order to find optimized MOS varactor layout designs that reduce the series resistance. An early example of this effort is the so-called “multi-finger” MOS varactor structure, which is depicted in FIG. 1. As shown, a multi-finger MOS varactor structure 100 is provided that includes an elongated, rectangular “active area” 110, which is typically embodied as an N-type well (N-well) disposed within a P-type semiconductor substrate (P-substrate) 130. The active area 110 includes a plurality of contact structures 111 connected therewith (typically heavily-doped N-type areas (N+ areas) are disposed in the N-well 110 at the location of each contact structure 111 to ensure adequate ohmic contact with the N-well 110). Disposed transversely across the elongated N-well is a plurality of elongated, rectangular gate structures 120. The gate structures 120 may be considered to resemble “fingers” stretched across the N-well 110, hence the common name multi-finger MOS varactor structure. Each gate structure 120 includes a plurality of gate contact structures 121. It should be noted that the gate contact structures 121 are disposed on the gate 120 so as not to overlie the active area N-well 110, but rather overlie the P-substrate 130 outside of the active area N-well 110. The reason for this placement of the gate contact structure 121 is to avoid the possibility of gate oxide damage to the gates 120 in the active area N-well 110 when forming the gate contact structure 121, as such gate oxide damage is known to cause device reliability problems.
Although the multi-finger layout design represents an improvement over conventional MOS varactor designs, the distance between the gate contact structures (i.e., the length of the gate through the active area N-well) remains undesirably high, which in turn causes an undesirably high gate resistance component of Rs, and thus a lower Q-factor of the MOS varactor. Other, more recent designs have attempted to reduce this length by providing “gate islands” within the active area N-well, such as the layout disclosed in FIGS. 1 and 2 of U.S. Patent Application Publication No. 2010/0244113 A1 to Rieh et al., but as noted above, due to the required placement of gate contacts overlying the active area N-well, this layout may suffer from reliability problems.
Accordingly, it would be desirable to provide MOS varactors with layout designs that lower the series resistance and increase the quality factor. It would also be desirable to provide MOS varactors with layout designs wherein the gate contact structures do not overlie the active area N-well to ensure device reliability. It would further be desirable to provide methods for fabricating such MOS varactors using conventional CMOS manufacturing processes and techniques. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.